An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration.
Hiroyuki KawaiYoshiki YamaguchiMoritoshi YasunagaKyrre GletteJim TørresenPublished in: FPT (2008)
Keyphrases
- shift register
- pattern recognition
- random number generator
- high speed
- hardware implementation
- low cost
- vlsi implementation
- signal processing
- single chip
- random number
- host computer
- programmable logic
- image processing
- circuit design
- hardware and software
- chip design
- low power
- real time
- evolvable hardware
- signal processor
- neural network
- field programmable gate array
- ibm zenterprise
- computer vision
- processing units
- high density
- low power consumption
- reconfigurable hardware
- machine learning
- ibm power processor
- image sensor
- analog vlsi
- embedded systems
- processor core
- computing systems
- real world