Login / Signup

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.

Rouwaida KanjRajiv V. JoshiJayakumaran SivagnanameJente B. KuangDhruva AcharyyaTuyet NguyenChandler McDowellSani R. Nassif
Published in: ISQED (2007)
Keyphrases
  • design considerations
  • leakage current
  • low voltage
  • random access memory
  • power line
  • pedagogical agents
  • power consumption
  • nm technology