A gate sizing and transistor fingering strategy for subthreshold CMOS circuits.
Morteza NabaviMaitham ShamsPublished in: IEICE Electron. Express (2012)
Keyphrases
- floating gate
- cmos technology
- high speed
- low voltage
- field effect transistors
- leakage current
- low power
- circuit design
- power dissipation
- focal plane
- chip design
- high density
- analog vlsi
- power consumption
- gate dielectrics
- nm technology
- low cost
- delay insensitive
- random access memory
- steady state
- logic circuits
- vlsi circuits
- infrared
- image sensor
- mathematical analysis
- design methodology