Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.
R. VenkatramanR. CastagnettiAndres TeeneBenjamin MbouombouoS. RameshPublished in: ISQED (2009)
Keyphrases
- single chip
- low power
- power consumption
- cmos technology
- power dissipation
- nm technology
- low cost
- high speed
- power management
- power reduction
- mixed signal
- silicon on insulator
- low voltage
- chip design
- embedded systems
- real time
- hardware architecture
- design considerations
- parallel processing
- power system
- transmission electron microscopy
- functional verification
- design process