: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits.

Ching-Hwa Cheng Chin-Hsien Wang

Published in: IEICE Trans. Electron. (2009)

Keyphrases

power consumption
digital circuits
duty cycle
clock gating
high speed
circuit design
low power
power reduction
power management
power supply
low voltage
cmos technology
power dissipation
low cost
clock frequency
electric field
mixed signal
functional decomposition
power system
power losses