Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet.
Anju P. JohnsonSayandeep SahaRajat Subhra ChakrabortyDebdeep MukhopadhyaySezer GörenPublished in: WESS (2014)
Keyphrases
- fault model
- software implementation
- hardware implementation
- field programmable gate array
- low cost
- high speed
- hardware architecture
- data acquisition
- real time
- embedded systems
- hardware design
- fault diagnosis
- advanced encryption standard
- dedicated hardware
- secret key
- hardware and software
- parallel hardware
- fault injection
- single chip
- manufacturing systems
- block cipher
- insertions and deletions
- countermeasures
- fault detection
- computer systems
- hardware architectures
- signal processing
- fpga implementation
- programmable logic
- parallel computing
- fpga hardware