Login / Signup
Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design.
Sungjae Kim
Hyungwoo Lee
Juho Kim
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2002)
Keyphrases
</>
circuit design
design automation
power consumption
digital circuits
information flow
power losses
neural network
high speed