Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations.
Yukinori MoritaTakahiro MoriShinji MigitaWataru MizubayashiAkihito TanabeKoichi FukudaTakashi MatsukawaKazuhiko EndoShin-ichi O'UchiYongxun LiuMeishoku MasaharaHiroyuki OtaPublished in: ESSDERC (2013)
Keyphrases
- electric field
- field effect transistors
- steady state
- multiple input
- high density
- space charge
- parallel processing
- significant improvement
- multi channel
- mathematical analysis
- parallel implementation
- massively parallel
- neural network
- parallel programming
- liquid crystal displays
- parallel computing
- tunnel boring machine
- parallel computation
- power consumption
- motion estimation
- genetic algorithm