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Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.

Timothy WheelerPaul S. GrahamBrent E. NelsonBrad L. Hutchings
Published in: FPL (2001)
Keyphrases
  • functional verification
  • design process
  • user interface
  • hardware design
  • hardware and software
  • design methodology
  • source code