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A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.

Zhiyuan SongAibin YanJie CuiZhili ChenXuejun LiXiaoqing WenChaoping LaiZhengfeng HuangHuaguo Liang
Published in: ITC-Asia (2019)
Keyphrases
  • high speed
  • knowledge based systems
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  • case study
  • design process
  • manufacturing cell
  • data sets
  • neural network
  • building blocks
  • software architecture
  • computer aided
  • single chip
  • cmos technology