A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip.
Xiang XiaoJaehwan John LeePublished in: IEEE Comput. Archit. Lett. (2007)
Keyphrases
- detection algorithm
- multithreading
- level parallelism
- highly parallel
- low cost
- single chip
- parallel hardware
- distributed memory
- multi core processors
- vlsi implementation
- floating point arithmetic
- parallel architectures
- shared memory
- multiprocessor systems
- memory bandwidth
- motion detection
- detection rate
- detection method
- parallel computing
- single processor
- massively parallel
- instruction set
- detection accuracy
- outlier detection
- vehicle detection
- corner detection
- programmable logic
- floating point
- circuit design
- parallel processing
- evolvable hardware
- message passing interface
- feature detection
- host computer
- chip design
- high speed
- parallel implementation
- moving objects
- ibm power processor
- parallel programming
- computer architecture
- computing systems
- commodity hardware
- image sensor
- shot boundary detection
- parallel execution
- graphics processing units
- real time
- harris corner
- memory access
- processing elements
- parallel architecture
- low power
- three dimensional