Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
Xuan WangJiang XuZhe WangHaoran LiPeng YangLuan H. K. DuongRafael K. V. MaedaZhifei WangPublished in: ACM J. Emerg. Technol. Comput. Syst. (2016)
Keyphrases
- ibm power processor
- high speed
- chip design
- level parallelism
- single chip
- memory subsystem
- functional verification
- multithreading
- low cost
- instruction set
- processor core
- analog vlsi
- power management
- error resilience
- low power
- silicon on insulator
- power consumption
- vlsi implementation
- embedded systems
- clock frequency
- power dissipation
- ibm zenterprise
- circuit design
- high density
- random access memory
- programmable logic
- cmos technology
- physical design