Test set compaction for combinational circuits.

Jau-Shien Chang Chen-Shang Lin

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1995)

Keyphrases

test set
logic circuits
asynchronous circuits
error rate
training set
test data
high speed
evaluation methodology
training data
class distribution
power dissipation
image database
training and test data
random selection