Chaotic Clock Driven Cryptographic Chip: Towards a DPA Resistant AES Processor.
Ali A. El-MoursyAbdollah Masoud DaryaAhmed S. ElwakilAbhinand JhaSohaib MajzoubPublished in: IEEE Trans. Emerg. Top. Comput. (2022)
Keyphrases
- high speed
- differential power analysis
- s box
- single chip
- advanced encryption standard
- clock frequency
- initial conditions
- smart card
- power analysis
- cryptographic algorithms
- low power
- data encryption standard
- block cipher
- power consumption
- ibm power processor
- processor core
- cellular automata
- functional verification
- chip design
- chaotic systems
- countermeasures
- random access memory
- secret key
- multithreading
- security protocols
- high density
- memory subsystem
- level parallelism
- encryption decryption
- ibm zenterprise
- parallel processing
- fpga device
- hash functions
- encryption algorithms
- memory access