Characterizing thread placement in the IBM POWER7 processor.
Stelios ManousopoulosMiquel MoretóRoberto GioiosaNectarios KozirisFrancisco J. CazorlaPublished in: IISWC (2012)
Keyphrases
- ibm power processor
- memory subsystem
- instruction set
- power management
- ibm zenterprise
- power consumption
- industry standard
- parallel processing
- floating point unit
- computational power
- error resilience
- high speed
- dynamic random access memory
- functional verification
- multithreading
- san jose
- silicon on insulator
- information systems
- chip design
- power distribution
- high level overview
- memory management
- high end
- computer architecture