Fast power density aware three-dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm.
Naorem Yaipharenba MeiteiKrishna Lal BaishnabGaurav TrivediPublished in: Int. J. Circuit Theory Appl. (2023)
Keyphrases
- integrated circuit
- genetic algorithm
- three dimensional
- fitness function
- bit rate
- evolutionary algorithm
- simulated annealing
- power consumption
- built in self test
- evolutionary search
- electron beam
- multi objective
- neural network
- video coding
- x ray
- rate distortion
- coding scheme
- bitstream
- error propagation
- evolutionary process
- printed circuit boards
- signal processing
- d objects