A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.

Hiroaki Yamaoka Makoto Ikeda Kunihiro Asada

Published in: ASP-DAC (2001)

Keyphrases

low power
logic circuits
high speed
charge coupled device
power consumption
low cost
gate array
image sensor
focal plane
functional decomposition
digital signal processing
charge coupled devices
tunnel diode
logic synthesis
power dissipation
real time
content addressable memory
image processing