Defect Oriented Testing of an ECL/CMOS Level Converter Circuit.

Min-Hsing P. Chen André Ivanov Sassan Tabatabaei

Published in: LATW (2000)

Keyphrases

low voltage
high speed
circuit design
single phase
analog vlsi
delay insensitive
power supply
power consumption
cmos technology
dc dc converter
random access memory
levels of abstraction
defect detection
design considerations
higher level
neural network
real time