Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design.
Sung-Mo KangRobert H. KrambeckHung-Fai Stephen LawAlexander D. LopezPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1983)
Keyphrases
- chip design
- random access memory
- micron cmos
- cmos technology
- circuit design
- design considerations
- nm technology
- low power
- power dissipation
- high speed
- physical design
- digital circuits
- logic circuits
- design methodology
- single chip
- flip flops
- low cost
- logical operations
- modal logic
- analog to digital converter
- layout design
- delay insensitive
- power consumption
- embedded dram
- built in self test
- control system
- low voltage
- memory access
- evolvable hardware
- modular design
- analog vlsi
- multithreading