Login / Signup
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.
Yu-Shih Su
Wing-Kai Hon
Cheng-Chih Yang
Shih-Chieh Chang
Yeong-Jar Chang
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2010)
Keyphrases
</>
duty cycle
power system
objective function
high speed
buffer size
data sets
genetic algorithm
production system
transmission line
low voltage