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Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time.
Hanwool Jeong
Juhyun Park
Seung Chul Song
Seong-Ook Jung
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
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low voltage
low power
cmos technology
power consumption
power management
high speed
low cost
design considerations
power line
power reduction
image processing
digital images
high density