An Accurate Interconnect Test Structure for Parasitic Validation in On-Chip Machine Learning Accelerators.
Chun-Chen LiuOscar LawFei LiPublished in: CoRR (2017)
Keyphrases
- machine learning
- high speed
- pattern recognition
- high density
- machine learning methods
- test cases
- knowledge representation
- knowledge acquisition
- artificial intelligence
- hierarchical structure
- machine learning algorithms
- text mining
- reinforcement learning
- high quality
- computer vision
- general purpose
- computer science
- statistical tests
- explanation based learning
- single chip
- ibm power processor