Clock skew minimization during FPGA placement.
Kai ZhuMartin D. F. WongPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)
Keyphrases
- high speed
- fpga device
- real time image processing
- objective function
- power consumption
- field programmable gate array
- hardware implementation
- signal processing
- low power consumption
- fpga implementation
- low power
- hardware architecture
- database
- low cost
- duty cycle
- digital signal
- convex functions
- parallel hardware
- software implementation
- hardware design
- parallel computing
- data acquisition
- website
- data sets