Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST.

Fahad Ahmed Linda Milor

Published in: VTS (2010)

Keyphrases

built in self test
power consumption
dynamic random access memory
design process
circuit design
data structure
low power consumption
modular design
physical design
single chip
monitoring system
low cost
main memory
power dissipation
high speed
random access memory
user interface
case study
speculative execution