Transistor and pin reordering for leakage reduction in CMOS circuits.
Jae Woong ChunC. Y. Roger ChenPublished in: Microelectron. J. (2016)
Keyphrases
- high speed
- circuit design
- power dissipation
- floating gate
- low power
- low voltage
- leakage current
- power reduction
- delay insensitive
- power consumption
- cmos technology
- analog vlsi
- vlsi circuits
- focal plane
- logic circuits
- low cost
- digital circuits
- chip design
- digital signal processing
- mixed signal
- reduction method
- genetic algorithm
- real time
- analog circuits
- power supply
- random access memory