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A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.
Mozhgan Mansuri
James E. Jaussi
Joseph T. Kennedy
Tzu-Chien Hsueh
Sudip Shekhar
Ganesh Balamurugan
Frank O'Mahony
Clark Roberts
Randy Mooney
Bryan Casper
Published in:
ISSCC (2013)
Keyphrases
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cmos technology
silicon on insulator
low cost
high speed
metal oxide semiconductor
nm technology
detection algorithm
power consumption
low power
hd video
lane detection
web scale
neural network
lightweight
analog vlsi
vlsi circuits
cellular automata
database systems