A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET.
Vinay KumarNikhil PuriSudhir KumarSumit SrivastavPublished in: VLSI Design (2017)
Keyphrases
- dynamic programming
- power consumption
- design considerations
- data structure
- design goals
- cmos technology
- management system
- key issues
- dynamic random access memory
- positive and negative
- hardware implementation
- network architecture
- software architecture
- reliability analysis
- random access memory
- embedded dram
- low power
- primal dual
- linear programming
- high speed
- leakage current
- nm technology
- neural network