Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures.
Aurélien AlacchiEdouard GiacominRoman GauchiSzymon KulisPierre-Emmanuel GaillardonPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2023)
Keyphrases
- low power
- high speed
- low cost
- low power consumption
- single chip
- gate array
- power consumption
- power reduction
- digital signal processing
- power dissipation
- digital signal processors
- high power
- wireless transmission
- field programmable gate array
- multi core processors
- error correction
- vlsi circuits
- mixed signal
- vlsi architecture
- error correcting
- main memory
- image sensor
- logic circuits
- power saving
- low density parity check
- nm technology
- hardware implementation
- real time