An adaptive Viterbi decoder on the dynamically reconfigurable processor.
Shohei AbeYohei HasegawaTakao ToiTakeshi InuoHideharu AmanoPublished in: FPT (2006)
Keyphrases
- noisy channel
- high speed
- low complexity
- hidden markov models
- decoding algorithm
- error detection
- parallel processing
- error concealment
- distributed memory
- computer architecture
- fpga implementation
- single processor
- viterbi algorithm
- parallel processors
- input output
- low cost
- instruction set
- motion estimation
- dynamic programming