A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%.
Yuji YokoyamaNobutaka ItohMasatoshi HasegawaMasahiro KatayamaHiroshi AkasakiMasayuki KanedaToshitsugu UedaYousuke TanakaEiji YamasakiMasaya TodokoroKeinosuke ToriyamaHiroshi MikiMasayoshi YagyuKazumasa TakashimaToru KobayashiSyuichi MiyaokaNobuo TambaPublished in: IEEE J. Solid State Circuits (2001)