Towards a tight hardness-randomness connection between permanent and arithmetic circuit identity testing.

Published in: Inf. Process. Lett. (2012)

Keyphrases

worst case
high speed
lower bound
computational complexity
upper bound
test cases
arithmetic operations
test set
micron cmos
data sets
frequency response
digital circuits
circuit design
floating point
low power
information theoretic
test data
np complete
access control
neural network