Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.
Roman GauchiValentin EgloffMaha KooliJean-Philippe NoëlBastien GiraudPascal VivetSubhasish MitraH.-P. CharlesPublished in: ISLPED (2020)
Keyphrases
- hardware implementation
- management system
- memory management
- power consumption
- embedded dram
- limited memory
- memory usage
- multi processor
- main memory
- low memory
- general purpose
- parallel processing
- processing elements
- level parallelism
- data flow
- computational power
- real time
- signal processing
- dynamic reconfiguration
- reconfigurable architecture
- input image
- dynamic random access memory