Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Houman HomayounShahin GolshanEli BozorgzadehAlexander V. VeidenbaumFadi J. KurdahiPublished in: ISQED (2010)
Keyphrases
- power consumption
- high speed
- low power
- optimization algorithm
- duty cycle
- optimization problems
- tree structure
- power dissipation
- global optimization
- computer networks
- program synthesis
- binary tree
- power management
- social networks
- spanning tree
- optimization model
- power losses
- optimization methods
- tree structures
- constrained optimization
- b tree
- index structure
- data structure