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23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.

Il-Min YiMin-Kyun ChaeSeok-Hun HyunSeung-Jun BaeJung-Hwan ChoiSeong-Jin JangByungsub KimJae-Yoon SimHong-June Park
Published in: ISSCC (2017)
Keyphrases
  • low voltage
  • high speed
  • low cost
  • cmos technology
  • user interface
  • main memory
  • power consumption
  • high density
  • mobile learning
  • mobile applications