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Wafer Level Accelerated test for ionic contamination control on VDMOS transistors in Bipolar/CMOS/DMOS.
Yannick Rey-Tauriac
M. Taurin
Olivier Bonnaud
Published in:
Microelectron. Reliab. (2001)
Keyphrases
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integrated circuit
power consumption
high density
low power
control system
circuit design
cmos technology
positive and negative
low cost
test cases
higher level
high speed
massively parallel
closed loop
control strategy
image processing
statistical significance
process control
control theory
low voltage
vlsi circuits