Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
Zhehui WangJiang XuXiaowen WuYaoyao YeWei ZhangMahdi NikdastXuan WangZhe WangPublished in: IEEE Trans. Computers (2014)
Keyphrases
- high speed
- low cost
- high bandwidth
- high density
- vlsi implementation
- circuit design
- multithreading
- physical design
- optimization algorithm
- single chip
- global optimization
- programmable logic
- modular design
- analog vlsi
- constrained optimization
- low power
- network design
- host computer
- social networks
- combinatorial optimization
- complex networks
- evolvable hardware
- network on chip