Automated SEU fault emulation using partial FPGA reconfiguration.
Uros LegatAnton BiasizzoFranc NovakPublished in: DDECS (2010)
Keyphrases
- semi automated
- fault diagnosis
- fully automated
- fault detection
- field programmable gate array
- real time
- data sets
- neural network
- high speed
- artificial intelligence
- data driven
- computer aided
- parallel hardware
- verilog hdl
- gate array
- systolic array
- partial information
- shared memory
- manufacturing systems
- signal processing
- low cost