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RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
Xiaojing Shang
Ming Ling
Shan Shen
Tianxiang Shao
Jun Yang
Published in:
MEMSYS (2019)
Keyphrases
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low voltage
random access memory
prefetching
power line
design considerations
query processing
object oriented
main memory
memory access
leakage current
real time
low cost
dynamic random access memory