Login / Signup

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.

Xiaojing ShangMing LingShan ShenTianxiang ShaoJun Yang
Published in: MEMSYS (2019)
Keyphrases
  • low voltage
  • random access memory
  • prefetching
  • power line
  • design considerations
  • query processing
  • object oriented
  • main memory
  • memory access
  • leakage current
  • real time
  • low cost
  • dynamic random access memory