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Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.
Saibal Mukhopadhyay
Hamid Mahmoodi
Kaushik Roy
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2008)
Keyphrases
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random access memory
power reduction
power consumption
cmos technology
linear array
human body
low power
database
machine learning
parametric models
data transmission
reduction method
parametric representation
transmission electron microscopy
embedded dram