A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.
Yudeng LinJianshi TangBin GaoQi QinQingtian ZhangHe QianHuaqiang WuPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2023)
Keyphrases
- high efficiency
- high speed
- high accuracy
- real and synthetic datasets
- real time
- low cost
- protection scheme
- vlsi implementation
- error rate
- error detection
- memory space
- data acquisition
- error bounds
- low power
- hardware and software
- result quality
- density based clustering
- massively parallel
- support vector
- training error
- high speed networks
- parallel architectures
- generalization error
- field programmable gate array
- parallel implementation
- estimation error
- hardware implementation
- image quality
- image processing
- real world