A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Hyun-Woo LeeYong-Hoon KimWon-Joo YunEun Young ParkKang Youl LeeJaeil KimKwang Hyun KimJongho JungKyung Whan KimNam Gyu RyeKwan-Weon KimJun Hyun ChunChulwoo KimYoung-Jung ChoiByong-Tae ChungJoong Sik KihPublished in: ISCAS (2010)