Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor.
Brian ZimmerPi-Feng ChiuBorivoje NikolicKrste AsanovicPublished in: A-SSCC (2016)
Keyphrases
- instruction set
- memory subsystem
- dynamic random access memory
- memory access
- embedded processors
- multithreading
- high speed
- processor core
- shared memory multiprocessors
- memory hierarchy
- ibm power processor
- application specific
- prefetching
- computation intensive
- data access
- cache misses
- floating point
- query processing
- shared memory multiprocessor
- database workloads
- memory management
- single chip
- computer architecture
- low power consumption
- power reduction
- hit rate
- main memory
- random access memory
- level parallelism
- parallel processing
- embedded systems
- computing power
- shared memory