Double Node Upsets Hardened Latch Circuits.
Yuanqing LiHaibin WangSuying YaoXi YanZhiyuan GaoJiangtao XuPublished in: J. Electron. Test. (2015)
Keyphrases
- power reduction
- low power
- power consumption
- high speed
- logic circuits
- flip flops
- digital circuits
- tunnel diode
- delay insensitive
- asynchronous circuits
- data sets
- graph structure
- machine learning
- databases
- high density
- network nodes
- power saving
- bayesian networks
- knowledge base
- information systems
- quantum computing
- logic synthesis