Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.
Takao NomuraRyo MoriMunehiro ItoKoji TakayanagiToshihiko OchiaiKazuki FukuokaKazuo OtsugaKoji NiiSadayuki MoritaTomoaki HashimotoTsuyoshi KidaJunichi YamadaHideki TanakaPublished in: CICC (2013)