Two-stage low power test data compression for digital VLSI circuits.
K. ThilagavathiS. SivananthamPublished in: Comput. Electr. Eng. (2018)
Keyphrases
- test data
- vlsi circuits
- low power
- mixed signal
- high speed
- power consumption
- low cost
- multi channel
- test set
- training data
- test cases
- single chip
- data sets
- cmos technology
- logic circuits
- digital circuits
- digital signal processing
- compression algorithm
- training and test data
- image compression
- low power consumption
- search based testing
- image sensor
- signal processing
- real time