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Layout-dependent fault analysis and test synthesis for CMOS circuits.

Marcel JacometWalter Guggenbühl
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1993)
Keyphrases
  • high speed
  • data analysis
  • quantitative analysis
  • neural network
  • statistical analysis
  • test cases
  • delay insensitive
  • database
  • image sequences
  • circuit design
  • multiple faults