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A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
Anselme Vignon
Stefan Cosemans
Wim Dehaene
Pol Marchal
Marco Facchini
Published in:
DATE (2009)
Keyphrases
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dynamic random access memory
management system
embedded dram
high speed
context aware
real time
context sensitive
contextual information
power consumption
low power
memory access
low voltage
main memory
random access memory
high density
conceptual model
neural network