A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS.
Immanuel RajaVishal KhatriZaira ZahirGaurab BanerjeePublished in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
- power consumption
- clock gating
- high speed
- cmos technology
- low power
- mixed signal
- clock frequency
- circuit design
- power dissipation
- power reduction
- vlsi circuits
- nm technology
- metal oxide semiconductor
- delay insensitive
- cmos image sensor
- low cost
- analog vlsi
- low voltage
- multiscale
- charge coupled device
- focal plane
- digital signal processing
- chip design
- framework for image segmentation
- silicon on insulator
- digital circuits
- fourier transform
- multispectral
- level set
- edge detection
- real time