A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.

Hyuk-Jun Sung Kwang Sub Yoon

Published in: ISCAS (2) (1999)

Keyphrases

high speed
low power
frame rate
wide range
real time
focal plane
data structure
fine grained
user input
high speed camera
data sets
signal processing
range data
concurrency control