Kwang Sub Yoon

Publication Activity (10 Years)

Years Active: 1995-2017
Publications (10 Years): 4

Top Topics

Delay Insensitive

Analog To Digital Converter

Top Venues

Publications

Jeong H. Choi, Kwang Sub Yoon
A CMOS third order ΔΣ modulator with inverter-based integrators. SoCC (2017)
Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, Kwang Sub Yoon
A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs. ISOCC (2016)
Tae-Heon Lee, Jong-Gu Kim, Kwang Sub Yoon
A CMOS buck converter with PFM / hysteretic mode. ISOCC (2016)
Seong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang
A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier. SoCC (2016)
Tae-Jin Chung, Kwang Sub Yoon
A CMOS hysteretic DC-DC buck converter with a low output ripple voltage. ISQED (2015)
Gi-Yoon Lee, Kwang Sub Yoon
Design of a low power CMOS 10bit flash-SAR ADC. SoCC (2014)
Kwang Sub Yoon, Keon Lee
A CMOS high dimming ratio power-LED driver with a preloading inductor current method. ISQED (2013)
Keon Lee, Dong-hun Lee, Su-hun Yang, Ji-hyun Park, Kwang Sub Yoon
Design of high dimming ratio power-LED driver with preloading inductor current methodology. ISOCC (2012)
Jinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee
Design of a 12-b asynchronous SAR CMOS ADC. ISOCC (2011)
Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. ISMVL (2004)
Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon
A dual band CMOS VCO with a balanced duty cycle buffer. ACM Great Lakes Symposium on VLSI (2003)
Hyuk-Jun Sung, Kwang Sub Yoon
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) (1999)
Jai-Sop Hyun, Kwang Sub Yoon
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. Great Lakes Symposium on VLSI (1996)
Jong Kug Seon, Kwang Sub Yoon
A Precision Output Conductance Model for Analog CMOS Circuit Simulations. ISCAS (1995)